FIG. 1 depicts a flowchart illustrating an IC design procedure used widely at present. First, designers utilize a tool program to perform RTL (Register Transfer Level) simulation and designate timing constraint for synthesis, so as to generate a netlist. The netlist is processed in the next step for physical design.
After the placement and routing procedures in the physical design are finished, the physical layout can be converted to a practical RC network by way of RC extraction software. The RC network is then processed with whole netlist delay calculation to generate timing data. Afterwards, timing verification and functional verification are performed to assure of correct design. If the verifications fail, designers will need to modify the netlist by way of an ECO (Engineering Change Order) process, and thus physical design and all the subsequent procedures need to start over. During the timing verification, a timing slack report will be obtained to determine whether the design is qualified or not and/or point out the failure parts of the circuit required to be modified. The result of the functional verification, on the other hand, can be realized with the RTL simulation and the netlist simulation.
As described above, all the steps beginning with the physical design and including placement, routing, whole netlist RC Extraction, whole netlist delay calculation and timing/functional verification of the ECO procedures need to be performed once again whenever the netlist is modified. Then, in response to the new timing slack report, all the above procedures may need to be performed again if the timing and/or function still fail in the verification. The repeated and complicated procedures will spend a lot of time and thus may delay the commercialization of products. For more and more sophisticated chip design, the whole netlist RC Extraction and whole netlist delay calculation particularly form a burden of designers.